Phased array with low-latency control interface

ABSTRACT

A phased array system has a plurality of beam-forming elements, and a plurality of beam-forming integrated circuits in communication with the beam-forming elements. Each beam-forming integrated circuit has a corresponding register bank with a plurality of addressable and programmable register sets. In addition, each beam-forming integrated circuit has at least two different types of beam-forming ports. Specifically, each beam-forming element has a serial data port for receiving serial messages, and a parallel mode data port for receiving broadcast messages. Both the serial and broadcast messages manage the data in its register bank. The beam-forming integrated circuits receive the broadcast messages in parallel with the other beam-forming integrated circuits, while the beam-forming integrated circuits receive the serial messages serially—sequentially with regard to other beam-forming integrated circuits.

RELATED APPLICATIONS

This application is a continuation of, and therefore claims priority to,U.S. patent application Ser. No. 16/501,456, filed on Mar. 7, 2019,which claims the benefit of U.S. Provisional Patent Application No.62/639,639, filed on Mar. 7, 2018, the entire contents of each of whichare incorporated herein by reference.

FIELD OF THE INVENTION

The invention generally relates to phased arrays and, more particularly,the invention relates to more efficiently managing beam-formingintegrated circuits.

BACKGROUND OF THE INVENTION

Active electronically steered antenna systems (“AESA systems,” a type of“phased array system”) form electronically steerable beams for a widevariety of radar and communications systems. To that end, AESA systemstypically have a plurality of beam-forming elements (e.g., antennas)that transmit and/or receive energy so that the signal on eachbeam-forming element can be coherently (i.e., in-phase and amplitude)combined (referred to herein as “beam-forming” or “beam steering”).Specifically, many AESA systems implement beam steering by providing aunique radio frequency (“RF”) phase shift and gain setting (phase andgain together constitute a complex beam weight) between eachbeam-forming element and a beam-forming or summation point.

The number and type of beam-forming elements in the phased array systemcan be selected or otherwise configured specifically for a givenapplication. A given application may have a specified minimumequivalent/effective isotropically radiated power (“EIRP”) fortransmitting signals. Additionally, or alternatively, a givenapplication may have a specified minimum G/T (analogous to asignal-to-noise ratio) for receiving signals, where:

-   -   G denotes the gain or directivity of an antenna, and    -   T denotes the total noise temperature of the receive system        including receiver noise figure, sky temperature, and feed loss        between the antenna and input low noise amplifier.

SUMMARY OF VARIOUS EMBODIMENTS

In accordance with one embodiment of the invention, a phased arraysystem has multiple beam-forming elements, and multiple beam-formingintegrated circuits in communication with the beam-forming elements.Each beam-forming integrated circuit can have a corresponding registerbank with a plurality of addressable and programmable register sets. Inaddition, each beam-forming integrated circuit can have at least twodifferent types of digital control interface ports. Specifically, eachbeam-forming element can have a serial data port for receiving serialmessages and a parallel mode data port for receiving broadcast messages.Both the serial and broadcast messages can manage the data in itsregister bank. The beam-forming integrated circuits can receive thebroadcast messages in parallel with the other beam-forming integratedcircuits. Additionally, the beam-forming integrated circuits can receivethe serial messages serially—sequentially with regard to otherbeam-forming integrated circuits (e.g., in a daisy chain configuration).

The phased array system also may have a controller that communicateswith the beam-forming integrated circuits. To that end, the controllermay have a parallel mode data output coupled with the parallel mode dataport of the beam-forming integrated circuits. Moreover, the beam-formingintegrated circuits can be switchable between any of a serial mode toreceive data in the serial data port only and a parallel mode to receivedata in the parallel mode data port only. In addition or instead, thebeam-forming integrated circuits can be switchable to or from a hybridmode that receives data in both a serial mode and a parallel mode.

Each of the programmable register sets may include a variety ofdifferent types of data to control the operation of the phased arraysystem. Among other things, the register sets may include one or more ofgain data corresponding to different beam characteristics of the phasedarray system, phase data corresponding to different beam characteristicsof the phased array system, three-dimensional beam steering data, andgain compensation data to compensate for temperature fluctuations of thesystem.

Each beam-forming integrated circuit can be implemented as anapplication specific integrated circuit (ASIC), field programmable gatearray (FPGA) or other circuitry. Moreover, each beam-forming integratedcircuit may include at least one of a clock input for receiving areference clock signal, a chip select input for enabling the integratedcircuit to be programmed, and a load enable input for loading data intothe programmable register sets.

The beam-forming integrated circuits may couple their serial ports toform a daisy chain. For example, for each beam-forming integratedcircuit, the serial data port may include both a serial data input and aserial data output. Thus, in some embodiments, the beam-formingintegrated circuits may include a first beam-forming integrated circuitand a second beam-forming integrated circuit. The serial data port ofthe first beam integrated circuit may include a first serial data inputand a first serial data output. In a corresponding manner, the serialdata port of the second beam-forming integrated circuit may include asecond serial data input and a second serial data output. As serialports, the first serial data output may be coupled with the secondserial data input, the first serial data input may be coupled with anupstream serial data output of another of the plurality of beam-formingintegrated circuits, and the second serial data output may be coupledwith a downstream serial data input of yet another of the plurality ofbeam-forming integrated circuits.

Each beam-forming integrated circuit may have multiple channels. Thus,the programmable register sets in each integrated circuit may have datafor each of the channels. In some implementations, the parallel andserial connections operate regardless of whether the system is in atransmit or receive mode. To that end, the beam-forming integratedcircuits may include one or more of receive only beam-forming integratedcircuits, transmit only beam-forming integrated circuits, and dualtransmit/receive beam-forming integrated circuits.

In accordance with another embodiment of the invention, a methodcontrols a phased array system having multiple beam-forming integratedcircuits. Each beam-forming integrated circuit can have a correspondingregister bank with addressable and programmable register sets, and twoports; namely, a serial data port for receiving serial messages thatmanage the data in its register bank and a parallel mode data port forreceiving broadcast messages that manage the data in its register bank.The method also distributes a broadcast message having register addressinformation to the beam-forming integrated circuits, via theirrespective parallel mode data ports, in parallel across a signaldistribution system. For each beam-forming integrated circuit, themethod retrieves data from addressable register sets having the addressof the register address information in the broadcast message, andapplies the retrieved data to change the operation of the phased arraysystem. In some embodiments, the method can further include setting thephased array system in a serial mode to receive data in the serial dataport only, a parallel mode to receive data in the parallel mode dataport only, or a hybrid mode that receives data in both the serial modeand the parallel mode.

In some embodiments, the programmable register sets of each beam-formingintegrated circuit includes one or more of gain data corresponding todifferent beam characteristics of the phased array system, phase datacorresponding to different beam characteristics of the phased arraysystem, three-dimensional beam steering data, gain compensation data tocompensate for temperature fluctuations of the system, and receiverlinearity data. The phased array system can have multiple beam-formingelements electrically coupled with the beam-forming integrated circuits.

In some embodiments, the method can include applying different amplitudeweights to different ones of the beam-forming elements. The method caninclude changing gain data as a function of temperature fluctuations inthe phased array system. In some embodiments, the method can furtherinclude receiving a serial message at the serial data port of a first ofthe beam-forming integrated circuits and forwarding the serial messageto a daisy chain of serial data ports of different beam-formingintegrated circuits. In some embodiments, the beam-forming integratedcircuits can include receive only beam-forming integrated circuits,transmit only beam-forming integrated circuits, dual transmit/receivebeam-forming integrated circuits, or any combination thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

Those skilled in the art should more fully appreciate advantages ofvarious embodiments of the invention from the following “Description ofIllustrative Embodiments,” discussed with reference to the drawingssummarized immediately below.

FIG. 1 schematically shows an active electronically steered antennasystem (“AESA system”) configured in accordance with illustrativeembodiments of the invention and communicating with a satellite.

FIGS. 2A and 2B schematically show generalized diagrams of an AESAsystem that may be configured in accordance with illustrativeembodiments of the invention.

FIG. 3A schematically shows a plan view of a laminar printed circuitboard portion of an AESA configured in accordance with illustrativeembodiments of the invention.

FIG. 3B schematically shows a close-up of a portion of the laminatedprinted circuit board of FIG. 3A.

FIG. 4 schematically shows a cross-sectional view of the laminatedprinted circuit board of FIG. 3A to highlight the mounting of itsintegrated circuits.

FIG. 5 schematically shows a generic representation of the AESA of FIG.1 in accordance with illustrative embodiments of the invention.

FIG. 6 schematically shows a generic representation of the signaldistribution system of the integrated circuits of the AESA in accordancewith illustrative embodiments of the invention.

FIG. 7 schematically shows additional details of a beam-formingintegrated circuit configured in accordance with illustrativeembodiments of the invention.

FIG. 8 generally shows an example of different functions and thestructure of a message implementing those functions in accordance withillustrative embodiments of the invention.

FIG. 9 generically shows an example of various addressable registersthat may be used with illustrative embodiments of the invention.

FIG. 10 shows a process of using the AESA in accordance withillustrative embodiments of the invention.

DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

In illustrative embodiments, an active electronically steered antennasystem can more rapidly change its operation during use. For example,the system can more rapidly change the direction and other beamcharacteristics during signal reception and/or signal transmission.Additionally, the system can more rapidly compensate for temperaturefluctuations. To that end, the system controls its beam-formingintegrated circuits with a parallel transmission to the relevantintegrated circuits. As described in the illustrated embodiments below,each of the beam-forming integrated circuits is configured to include aparallel mode data interface port for receiving control messagesbroadcast from a controller in order to change certain characteristicsof a beam produced by beam-forming elements of the antenna system morerapidly than prior art methods known to the inventors.

Details of illustrative embodiments are discussed below.

FIG. 1 schematically shows an active electronically steered antennasystem (“AESA system 10”) configured in accordance with illustrativeembodiments of the invention and communicating with an orbitingsatellite 12. A phased array (discussed below and identified byreference number “10A”) implements the primary functionality of the AESAsystem 10. Specifically, as known by those skilled in the art, thephased array forms one or more of a plurality of electronicallysteerable beams that can be used for a wide variety of applications. Asa satellite communication system, for example, the AESA system 10preferably is configured operate at one or more satellite frequencies.Among others, those frequencies may include the Ka-band, Ku-band, and/orX-band.

The satellite communication system may be part of a cellular networkoperating under a known cellular protocol, such as the 3G, 4G, or 5Gprotocols. Accordingly, in addition to communicating with satellites,the system may communicate with earth-bound devices, such as smartphonesor other mobile devices, using any of the 3G, 4G, or 5G protocols. Asanother example, the satellite communication system may transmit/receiveinformation between aircraft and air traffic control systems. Of course,those skilled in the art may use the AESA system 10 (implementing thenoted phased array 10A) in a wide variety of other applications, such asbroadcasting, optics, radar, etc. Some embodiments may be configured fornon-satellite communications and instead communicate with other devices,such as smartphones (e.g., using 4G or 5G protocols). Accordingly,discussion of communication with orbiting satellites 12 is not intendedto limit all embodiments of the invention.

FIGS. 2A and 2B schematically show generalized diagrams of the AESAsystem 10 configured in accordance with illustrative embodiments of theinvention. Specifically, FIG. 2A schematically shows a block diagram ofthe AESA system 10, while FIG. 2B schematically shows a cross-sectionalview of a small portion of the same AESA system 10 across line B-B. Thislatter view shows a single silicon integrated circuit 14 mounted onto asubstrate 16 between two transmit, receive, and/or dual transmit/receiveelements 18, i.e., on the same side of a supporting substrate 16 andjuxtaposed with the two elements 18. In alternative embodiments,however, the integrated circuit 14 could be on the other side/surface ofthe substrate 16. The AESA system 10 also has a polarizer 20 toselectively filter signals to and from the phased array 10A, and aradome 22 to environmentally protect the phased array of the system 10.A separate antenna controller 24 (FIG. 2B) electrically connects withthe phased array to calculate beam steering vectors for the overallphased array, and to provide other control functions.

FIG. 3A schematically shows a plan view of a primary portion of an AESAsystem 10 that may be configured in accordance with illustrativeembodiments of the invention. In a similar manner, FIG. 3B schematicallyshows a close-up of a portion of the phased array 10A of FIG. 3A.

Specifically, the AESA system 10 of FIG. 3A is implemented as a laminarphased array 10A having a laminated printed circuit board 16 (i.e.,acting as the substrate and also identified by reference number “16”)supporting the above noted plurality of elements 18 and integratedcircuits 14. The elements 18 preferably are formed as a plurality ofsquare or rectangular patch antennas oriented in a triangular patcharray configuration. In other words, each element 18 forms a trianglewith two other adjacent elements 18. When compared to a rectangularlattice configuration, this triangular lattice configuration requiresfewer elements 18 (e.g., about 15 percent fewer in some implementations)for a given grating lobe free scan volume. Other embodiments, however,may use other lattice configurations, such as a pentagonal configurationor a hexagonal configuration. Moreover, despite requiring more elements18, some embodiments may use a rectangular lattice configuration. Likeother similar phased arrays, the printed circuit board 16 also may havea ground plane (not shown) that electrically and magnetically cooperateswith the elements 18 to facilitate operation.

Indeed, the array shown in FIGS. 3A and 3B is a small phased array 10A.Those skilled in the art can apply principles of illustrativeembodiments to laminar phased arrays 10A with hundreds, or eventhousands, of elements 18 and integrated circuits 14. In a similarmanner, those skilled in the art can apply various embodiments tosmaller phased arrays 10A.

As a patch array, the elements 18 have a low profile. Specifically, asknown by those skilled in the art, a patch antenna (i.e., the element18) typically is mounted on a flat surface and includes a flatrectangular sheet of metal (known as the patch and noted above) mountedover a larger sheet of metal known as a “ground plane.” A dielectriclayer between the two metal regions electrically isolates the two sheetsto prevent direct conduction. When energized, the patch and ground planetogether produce a radiating electric field. Illustrative embodimentsmay form the patch antennas using conventional semiconductor fabricationprocesses, such as by depositing one or more successive metal layers onthe printed circuit board 16. Accordingly, using such fabricationprocesses, each radiating element 18 in the phased array 10A should havea very low profile.

The phased array 10A can have one or more of any of a variety ofdifferent functional types of elements 18. For example, the phased array10A can have transmit-only elements 18, receive-only elements 18, and/ordual mode receive and transmit elements 18 (referred to as “dual-modeelements 18”). The transmit-only elements 18 are configured to transmitoutgoing signals (e.g., burst signals) only, while the receive-onlyelements 18 are configured to receive incoming signals only. Incontrast, the dual-mode elements 18 are configured to either transmitoutgoing burst signals, or receive incoming signals, depending on themode of the phased array 10A at the time of the operation. Specifically,when using dual-mode elements 18, the phased array 10A can be in eithera transmit mode, or a receive mode. The noted controller 24, at least inpart, controls the mode and operation of the phased array 10A, as wellas other array functions.

The AESA system 10 has a plurality of the above noted integratedcircuits 14 (mentioned above with regard to FIG. 2B) for controllingoperation of the elements 18. Those skilled in the art often refer tothese integrated circuits 14 as “beam steering integrated circuits,” or“beam-forming integrated circuits.”

Each integrated circuit 14 preferably is configured with at least theminimum number of functions to accomplish the desired effect. Indeed,integrated circuits 14 for dual mode elements 18 are expected to havesome different functionality than that of the integrated circuits 14 forthe transmit-only elements 18 or receive-only elements 18. Accordingly,integrated circuits 14 for such non-dual-mode elements 18 typically havea smaller footprint than the integrated circuits 14 that control thedual-mode elements 18. Despite that, some or all types of integratedcircuits 14 fabricated for the phased array 10A can be modified to havea smaller footprint.

As an example, depending on its role in the phased array 10A, eachintegrated circuit 14 may include some or all of the followingfunctions:

-   -   phase shifting,    -   amplitude controlling/beam weighting,    -   switching between transmit mode and receive mode,    -   output amplification to amplify output signals to the elements        18,    -   input amplification for received RF signals (e.g., signals        received from the satellite 12), and    -   power combining/summing and splitting between elements 18.

Indeed, some embodiments of the integrated circuits 14 may haveadditional or different functionality, although illustrative embodimentsare expected to operate satisfactorily with the above noted functions.Those skilled in the art can configure the integrated circuits 14 in anyof a wide variety of manners to perform those functions. For example,the input amplification may be performed by a low noise amplifier, thephase shifting may use conventional active phase shifters, and theswitching functionality may be implemented using conventionaltransistor-based switches.

Each integrated circuit 14 preferably operates on at least one element18 in the array. For example, one integrated circuit 14 can operate ontwo or four different elements 18. Of course, those skilled in the artcan adjust the number of elements 18 sharing an integrated circuit 14based upon the application. For example, a single integrated circuit 14can control two elements 18, three elements 18, five elements 18, sixelements 18, seven elements 18, eight elements 18, etc., or some rangeof elements 18. Sharing the integrated circuits 14 between multipleelements 18 in this manner reduces the required total number ofintegrated circuits 14, correspondingly reducing the required size ofthe printed circuit board 16.

As noted above, the dual-mode elements 18 may operate in a transmitmode, or a receive mode. To that end, the integrated circuits 14 maygenerate time division diplex or duplex waveforms so that a singleaperture or phased array 10A can be used for both transmitting andreceiving. In a similar manner, some embodiments may eliminate acommonly included transmit/receive switch in the side arms of theintegrated circuit 14. Instead, such embodiments may duplex at theelement 18. This process can be performed by isolating one of theelements 18 between transmit and receive by an orthogonal feedconnection.

RF interconnect and/or beam-forming lines 26 electrically connect theintegrated circuits 14 to their respective elements 18. To furtherminimize the feed loss, illustrative embodiments mount the integratedcircuits 14 as close to their respective elements 18 as possible.Specifically, this close proximity preferably reduces RF interconnectline lengths, reducing the feed loss. To that end, each integratedcircuit 14 preferably is packaged either in a flip-chipped configurationusing wafer level chip scale packaging (WLCSP), or a traditionalpackage, such as quad flat no-leads package (QFN package). While othertypes of packaging may suffice, WLCSP techniques are preferred tominimize real estate on the substrate 16.

In addition to reducing feed loss, using WLCSP techniques reduces theoverall footprint of the integrated circuits 14, enabling them to bemounted on the top face of the printed circuit board 16 with theelements 18—providing more surface area for the elements 18.

It should be reiterated that although FIGS. 3A and 3B show the AESAsystem 10 with some specificity (e.g., the layout of the elements 18 andintegrated circuits 14), those skilled in the art may apply illustrativeembodiments to other implementations. For example, as noted above, eachintegrated circuit 14 can connect to more or fewer elements 18, or thelattice configuration can be different. Accordingly, discussion of thespecific configuration of the AESA system 10 of FIG. 3A (and otherfigures) is for convenience only and not intended to limit allembodiments.

FIG. 4 schematically shows a cross-sectional view of the layout ofcomponents on the laminated printed circuit board 16 of 3A to highlightthe flip-chip mounting of its integrated circuits 14. The integratedcircuit 14 in this drawing intentionally is enlarged to show details ofa flip-chip mounting technique. Unlike techniques that permitinput/output (“I/O”) only on the edge of the integrated circuit 14,flip-chip mounting permits I/O on interior portions of the integratedcircuit 14.

As shown, the integrated circuit 14 has a plurality of pads 28 alignedwith a plurality of corresponding pads 28 on the printed circuit board16. These opposing pads 28 on the integrated circuit 14 and the printedcircuit board 16 may be considered to form pairs of pads 28. Solder 30(e.g., solder balls) electrically connects each the pads incorresponding pairs of pads 28. Interconnect lines, traces, and otherelectrical interconnects on/in the printed circuit board 16 (e.g., lines26) thus permit the integrated circuit 14 to communicate with otherelements 18 through this electrical interface.

The embodiment shown in FIG. 4 forms a space or void (identified byreference number “32”) between the bottom of the integrated circuit 14(from the perspective of this drawing) and the top surface of theprinted circuit board 16. This space 32 may remain an openvoid—containing no material. Some embodiments may take advantage of thisextra space 32 to add further components, such as additional circuitelements, without requiring more circuit board space. Alternatively,this space 32 may contain fill material (not shown) for furtherstability and thermal management of the integrated circuit 14.

Other embodiments, however, still may use similar integrated circuits14, but not use flip-chip mounting techniques. Instead, other mountingtechniques may couple the integrated circuits 14 with the substrate 16.Among other things, those techniques may incorporate surface mounting,or wirebond mounting with the integrated circuit 14 rotated 180 degreesfrom the orientation of FIG. 4 . Similar embodiments may useconventional packaging, such as quad-flat leadframe packages (i.e.,“QFN” packages). Accordingly, discussion of flip chip mountingtechniques is but one of a variety of different techniques that may beused with various embodiments of the invention.

FIG. 5 schematically shows phased array 10A in accordance with certainexemplary embodiments. Among other things, the phased array 10A includesthe noted beam-forming controller 24 for controlling a number ofbeam-forming integrated circuits 14, and a signal distribution system33. As shown in this example, the beam-forming integrated circuits 14and the beam-forming controller 24 can be implemented as applicationspecific integrated circuits (ASICs). However, those skilled in the artwill recognize the beam-forming integrated circuits 14 and thecontroller 24 can be implemented using field programmable gate arrays(FPGAs) or other electronic circuitry.

Each of the beam-forming integrated circuits 14 can support one or morebeam-forming elements 18 (e.g., RF antennas for operation in theexemplary radar or 5G system). In this example, the phased array 10Aincludes X beam-forming integrated circuits 14 ₁ to 14 _(X), with eachof the beam-forming integrated circuits 14 supporting Y beam-formingelements 18. For example, the integrated circuit 14 ₁ is electricallycoupled to beam-forming elements 18 ₁₁ to 18 _(1Y), and the integratedcircuit 14 _(X) is electrically coupled to beam-forming elements 18_(X1) to 18 _(XY). Thus, the phased array 10A includes (X*Y)beam-forming elements 18, where X and Y are greater than one.

The phased array 10A of FIG. 5 can be used for transmitting and/orreceiving a beam-formed signal via the beam-forming elements 18. Thus,the signal distribution system 33 may be configured to distribute abeam-forming signal STX to each of the beam-forming integrated circuits14 and/or to produce a combined beam-formed signal S_(RX) from signalsreceived from the beam-forming integrated circuits 14.

In accordance with illustrative embodiments of the invention, each ofthe integrated circuits 14 of the phased array 10A (or sub-arraythereof) has an input connected in parallel to the same input of theother integrated circuits 14 for receiving broadcast messages from thecontroller 24. This input, referred to herein as a “parallel mode datainput,” allows the controller 24 to transmit a single control message(e.g., CTRL) in parallel to all of the beam-forming integrated circuitsincluded in the array or sub-array. Accordingly, during operation, thecontroller 24 can change an operating parameter of the beam-formingintegrated circuits 14, such as a beam weighting parameter, much morerapidly than prior art methods known to the inventors. For example, inconventional antenna systems, beam-forming integrated circuits aretypically programmed in series.

To those ends, FIG. 6 schematically shows an interconnection and pindrawing identifying the various ports of four beam-forming integratedcircuits 14 ₁′, 14 ₂′, 14 ₃′, and 14 ₄′ (collectively, integratedcircuits 14′) configured in accordance with illustrative embodiments. Itshould be noted that four integrated circuits 14′ are shown forconvenience only and thus, those skilled in the art can apply thistechnique to more or fewer integrated circuits 14′.

Importantly, each of the beam-forming integrated circuits 14′ has aparallel mode data input (“spi_pdi”) As shown, a data interconnect 26 a′(e.g., a wire or other conductor) electrically connects a parallel modedata output (“spi_pdo”) of the controller 24′ in parallel with all fourparallel mode data inputs (“spi_pdi”) of the four integrated circuits14′. Accordingly, the controller 24′ can transmit a single controlmessage from its parallel mode data output (“spi_pdo”) over the datainterconnect 26 a′ for parallel reception at the parallel mode datainput (“spd_pdi”) of all of the beam-forming integrated circuits 14′.For example, using this broadcast transmission technique, the phasedarray 10A can be configured more rapidly to move its beam or otherwisechange one or more other beam characteristics, e.g., to track asatellite or orbiting object.

Each of the beam-forming integrated circuits 14′ preferably has one ormore additional interfaces for receiving other kinds of signals from thecontroller 24′. Among others, those interfaces can include:

-   -   a clock input (“spi_clk”) to receive timing signals,    -   a serial data input (“spi_sdi”) to receive data serially from        the controller 24′ or another beam-forming integrated circuit        14′,    -   a serial data output (“spi_sdo”) to transmit data serially to        another beam-forming integrated circuit 14′ or the controller        24′,    -   a chip select input (“spi_csb”) for enabling the integrated        circuit 14′ to be programmed, and    -   a load enable input (“spi_ldb”) for loading data into the        programmable register sets.

Indeed, some embodiments of the beam-forming integrated circuits 14′ mayhave additional ports for additional functionality. In a similar manner,some embodiments of the beam-forming integrated circuits 14′ may have asubset of various combinations these ports. Accordingly, discussion ofthe specific ports is by example only and not intended to limit variousembodiments the invention.

As discussed in more detail below, in some embodiments, the phased array10A can be operated in a serial mode, a parallel mode, or a hybrid mode.To those ends, as shown in the illustrated embodiment, the controller24′ and the beam-forming integrated circuits 14′ can be arranged in adaisy chain configuration using the serial data interfaces “spi_sdi” and“spi_sdo” to facilitate operation in “serial mode.” For purposes ofexample only, a first daisy chain is formed by the controller 24′ andthe beam-forming integrated circuits 14 ₁′ and 14 ₂′, and a second daisychain is formed by the controller 24′ and the beam-forming integratedcircuits 14 ₃′ and 14 ₄′.

When operating the first daisy chain in serial mode, the controller 24′can serially write a control message containing data for subsequentconfiguration of the beam-forming integrated circuits 14 ₁′ and 14 ₂′ ofthe first daisy chain. The control message can be clocked from theserial data output “spi_sdo” of the controller 24′ through the serialdata input “spi_sdi” of the first integrated circuit 14 ₁′. The serialdata output “spi_sdo” of the first integrated circuit 14 ₁′ successivelyfeeds the serial data input “spi_sdi” of the next integrated circuit 14₂′ until the control message is clocked across all of the beam-formingintegrated circuits 14 ₁′ and 14 ₂′ in the chain. Thereafter, thecontroller 24′ can transmit a load enable signal to the load enableinput “spi_ldb” of the respective integrated circuits 14 ₁′ and 14 ₂′that causes the data included in the control message to be written intoan internal register address specified in the control message.

FIG. 7 schematically shows additional details of the beam-formingintegrated circuit 14′ configured in accordance with illustrativeembodiments of the invention. As shown, the integrated circuit 14′includes a serial data interface port 60 and a “parallel mode” datainterface port 62. The serial data interface port 60 receives serialmessages via the serial data input “spi_sdi” and transmits serialmessages via the serial data output “spi_sdo.” The parallel mode datainterface port 62 receives data via the parallel mode data input“spi_pdi,”

In some embodiments, the “parallel mode” data interface port 62 can beimplemented as a serial data interface port, such as a Serial PeripheralInterface (SPI) port. SPI ports typically exhibit low power dissipationand complexity. SPI ports are also typically easier to interface withcommercially available controller FPGAs and ASICs, which usually havemany General Purpose Input/Output (GPIO) and SPI ports. In someembodiments, the parallel mode data interface port 62 can be paralleldata interface port, such as a Peripheral Component Interconnect (PCI)port. However, parallel ports typically exhibit higher powerdissipation, require more complex circuitry/implementation, and havemany interface pins which increases the cost of the integrated circuit.

Each of the data interface ports 60 and 62 is connected to memory forstoring various different operating parameters of the phased array 10A.In illustrative embodiments, the memory is implemented in the form of aregister bank having addressable and programmable register sets 64.Accordingly, among other functions, the serial data interface port 60and/or the parallel mode data interface port 62, as well as logicassociated with those ports 60 and 62, may forward control/data messagesto one or more of the register sets 64, thereby causing an intendedchange in the operation of the phased array 10A. For example, theparallel mode data interface port 62 may receive a message indicating achange of address to retrieve beam steering data from a specificregister of the register sets 64. This new beam steering data may beused to transmit a beam along a different trajectory. Accordingly, theregistry sets 64 are used to configure the beam-forming channels 68 thatare electrically coupled to one or more of the beam-forming elements 18.

Those skilled in the art will recognize that the beam-forming channels68 can include a transmit chain, a receive chain, or both. A transmitchain can be configured to transmit signals through a corresponding oneof the beam-forming elements 18. A receive chain can be configured toreceive signals from a corresponding one of the beam-forming elements18. Each chain can include various components including a signalattenuator, a phase shifter, a frequency converter, and/or a gainamplifier (not shown). The beam steering data retrieved from one or moreof the register sets 64 can be used to configure one or more of thecomponents of the beam-forming channels 68.

The beam-forming integrated circuit 14′ also may include an internalsignal distribution system 33A for transmitting or receiving a commonbeam-forming signal to and/or from each of Y beam-forming channels 68.Each register set 64 thus has data for configuring each of the Ybeam-forming channels 64. Each register set 64 thus may include one ormore registers for programming the complex beam weight of acorresponding beam-forming channel 68. For example, each register set 64may include a single register that stores a word including bothgain/amplitude and phase parameters for its corresponding beam-formingchannel. Alternatively, each register set 64 may include separateregisters that are used to store separate gain/amplitude and phaseparameters for a corresponding one of the beam-forming channels 68.

Each beam-forming integrated circuit 14′ may operate in any of threemodes, and may be switchable between each of these modes:

-   -   serial mode, which uses the serial data interface port 60 only    -   parallel mode, which uses the parallel mode data interface port        62 only,    -   hybrid mode, which uses both the serial data interface port 60        and the parallel mode data interface port 62.

For example, in “serial mode” operation, serial data received on theserial data input “spi_sdi” is shifted onto the serial data interfaceport 60. The serial data interface port 60 can write that data to one ormore of the register sets 64 and/or can shift that data out through theserial data output “spi_sdo” to another integrated circuit 14′ or thecontroller 24′. As discussed above, with respect to FIG. 6 , “serialmode” operation can be useful, if not necessary, to pre-program theregister sets 64 of a daisy-chained set of integrated circuits withunique data.

In “parallel mode” operation, serial data received from the controller24′ on the parallel mode data input “spi_pdi” is shifted into the“parallel mode” data interface port 62. The parallel mode data interfaceport 62 can write that data to one or more of the register sets 64.Thus, operating the integrated circuits 14′ in parallel mode allows thecontroller 24′ to broadcast commands in parallel to all beam-formingintegrated circuits 14′ in the array, such as but not limited to a setof fast-access write commands that enable fast beam switching, amongother things.

“Hybrid mode” operations combines serial mode and parallel modeoperation into a single transaction. For example, “hybrid mode”operation may be used to provide a serial mode write/read of data wordsthrough all the beam-forming integrated circuits 14′ in a daisy chain,preceded by a single control word sent in the parallel mode. In thiscase, the transaction may start in parallel mode using the parallel modedata interface port 62. After the control word is latched, however, thedata shifts through the daisy chain of beam-forming integrated circuits14′ using the serial data interface port 60 of the respective integratedcircuits. Thus, hybrid mode has the advantage of transmitting thecontrol word only once.

Those skilled in the art will recognize that modern phased arrays,especially those used in the latest generation of communication systems,often require the capability of switching between different beamdirections at a high speed (sometimes referred to herein as “fast beamswitching” or FBS). The on-chip programmable register banks included inthe beam-forming integrated circuits 14′ help to enable thisfunctionality. Typically, the register sets 64 are programmed at startup before operation begins. In some embodiments, each register set 64may store phase-shift settings and optionally gain/amplitude settingsfor programming each beam-forming channel 68 and correspondingbeam-forming element(s) 18 in the phased array 10A at runtime. Forexample, each of group of beaming channel/element settings maycorrespond to a different array beam direction. Other embodiments,however, may program these memories at a later time.

As suggested above, the registers in the register sets 64 are typicallyaccessed by means of an address word. In illustrative embodiments, eachaddress corresponds to a different beam direction for the phased array10A. By changing the address, e.g., through the parallel mode datainterface port 62 or the serial data interface port 60, the phased array10A can more rapidly retrieve different data to change the direction ofthe beam. As discussed above, by controlling the beam-forming integratedcircuits 14′ in parallel mode, the beam direction can be changedrapidly, resulting in shorter beam switching times. For example, in someembodiments, a phased array 10A can be configured to switch betweenapproximately 512 beam directions, such that the phased array 10A can beswitched between any two beam directions in less than 15 clock cycles(e.g., measured in periods of a clock signals transmitted to the clockinput “spi_clk” of the respective integrated circuits)

Illustrative embodiments can also enable three-dimensional beam steering(TDBS). Specifically, three-dimensional beam steering, as known by thoseskilled in the art, refers to the capability of applying differentamplitude weights to different beam-forming elements 18 in the phasedarray 10A. This technique therefore can shape the array beam, forexample, to reduce the side-lobe level. Individual beam-forming elements18 can be switched off to reduce DC power consumption, which effectivelyresizes the phased array 10A. Three-dimensional beam steering is oftenconsidered to encompass a number of features, such as array tapercontrol, aperture control/reconfiguration, and dynamic array resizing.The amplitude weight settings can be stored in the noted register sets64 to enable fast programming. Moreover, the amplitude weights can bestored in the same or different registers than those of other operatingparameters, such as fast beam steering registers.

Illustrative embodiments can also utilize the parallel mode datainterface port 62 to optimize temperature compensation processes. Forexample, the beam-forming integrated circuits 14′ may modify certainoperating parameters (e.g., gain settings) for each beam-forming channel68 and corresponding beam-forming element(s) 18 in the phased array 10Aas a function of the temperature. To that end, the system 10 may havevariable gain RF circuitry that can be programmed using the serial datainterface port 60 and/or the parallel mode data interface port 62. Aswith the various configuration settings for three-dimensional beamsteering and fast beam switching, the different gain settings that maybe required to compensate the gain settings as a function of temperaturemay be stored in the same or different memories or registers than thoseof the other types of data. Use of the parallel mode data port 62enables the array gain to be rapidly adjusted as the temperature of thearray varies. This feature also can compensate for temperature gradientsacross the beam-forming integrated circuits 14′ in the phased array 10Aby programming the gain setting of each beam-forming integrated circuit14′ based upon its position on the phased array 10A.

Indeed, those skilled in the art may change other operating parametersof the phased array 10A in additional ways. For example, the parallelmode can be used to rapidly control receiver linearity. Morespecifically, in common communication systems, programmable receiverlinearity is desirable to control the signal-to-noise ratio at thereceiver output as a function of the input power. Accordingly, when anRF input signal received by the beam-forming elements 18 is weak, highgain and low noise figure at the receiver is desired. Conversely, when areceived input signal strong, a lower gain and higher noise figure canbe tolerated and typically is desired to maintain signal fidelity.

Next-generation communication systems, based on phased arrays, mayrequire the receiver to communicate with multiple transmitters adifferent distances from the receiver. If one of the transmitters ismuch closer to the receiver than the other transmitter, then the powerof the two signals may vary by an order of magnitude relative to eachother. To maintain communication with both transmitters, the receivergain therefore may be adjusted on a frame-to-frame basis (i.e., eachframe corresponding to one transmitter). For example, in someembodiments, the beam-forming integrated circuits 14′ can be operated inparallel mode to reduce the gain of all of the integrated circuits ofthe phased array 10A, while improving receiver linearity. Since thelength time needed to perform a parallel mode transaction is typicallymuch shorter than typical communication frame length, receiver gain canbe changed on a frame-to-frame basis.

Discussion of specific uses of the serial data interface port 60, theparallel mode interface port 62 in conjunction with the programmableregister sets 64 disclosed here are illustrative and not intended tolimit all embodiments of the invention.

Various embodiments apply to either or both the transmit and receivemodes of the phased array 10A. In fact, the beam-forming integratedcircuit 14′ may have features that provide more flexibility in thevarious operations for both modes. For example, the same or differentregister sets 64 may be used for either or both the transmit and receivemodes. Similarly, both modes may share addresses or use separateaddresses.

FIG. 8 shows an example of how different functions may be implemented inillustrative embodiments of the phased array 10A. In this example,control messages are shown in which the first two or four bits may actas a control word to identify the function, while the remainder of themessage includes a data word for that identified function.

In the illustrated embodiments, control message 80 shows an exemplaryformat for performing a “serial mode” transaction using the serial datainterface port 60 of a single beam-forming integrated circuit 14′. Asshown, the control word 81 (“00”) identifies the function as a serialwrite command for one integrated circuit and the data word 82 includes a48-bit serial data to be written at a specified 10-bit register address.

Control message 83 shows an exemplary format for performing a “serialmode” transaction using the serial data interface ports 60 for a set ofdaisy-chained beam-forming integrated circuits 14′. As shown, thecontrol message 83 includes multiple control messages 80 for seriallyprogramming each of the respective integrated circuits 14′ in the chain.Each of the individual control messages 80 within the control message 83can include the same or different 48-bit serial data to be written atthe same or different 10-bit register address in the respectiveintegrated circuits.

Control message 84 shows an exemplary format for performing a “hybridmode” transaction using the serial data interface ports 60 and theparallel mode data interface ports 62 for a set of daisy-chainedbeam-forming integrated circuits 14′. As shown, the control word 85(“1000”), which identifies the function as a hybrid write command, isbroadcast over the parallel mode data interface ports 62 of therespective beam-forming integrated circuits 14′. The data word 86includes a 48-bit serial data to be written at a specified 10-bitregister address using the serial data interface ports 60 of eachintegrated circuit.

Control message 87 shows an exemplary format for performing a “parallelmode” transaction using the parallel mode data interface ports 62 of aset of beam-forming integrated circuits 14′. As shown, the control word88 (“1001”) identifies the function as a parallel write command that isbroadcast to all of the beam-forming integrated circuits 14′ in the set.The data word 89 includes a 48-bit serial data to be written at aspecified 10-bit register address in each of the integrated circuits. Inthis example, the same data is written to each of the parallel-connectedintegrated circuits.

Control message 90 shows an exemplary format for performing a “parallelmode” transaction using the parallel mode data interface ports 62 of aset of beam-forming integrated circuits 14′. As shown, the control word91 (“1010”) identifies the function as a 3D receive beam steering switchcommand that is broadcast to all of the beam-forming integrated circuits14′ in the set. In this example, the data word 92 includes a 6-bitregister address (i.e., RXTDBS_ADDR) from which to retrieve a gainsetting or other beam-forming data to change the shape or othercharacteristic of the receive beam. Although the beam-forming integratedcircuits 14′ access the same register address in one or more of itsregister sets 64, the gain settings configured for each beam-formingchannel 68 and corresponding beam-forming element 18 can be different.The data word 92 also includes an additional 3-bit gain setting value(i.e., RXIP3[2:0]) for changing the receiver linearity associated withthe beam-forming channels 68 and corresponding beam-forming elements 18in each of the integrated circuits.

Control messages 93, 94, 95, 96, and 97 show exemplary formats forperforming other “parallel mode” transactions to change theconfiguration settings of the beam-forming channels 68 and correspondingbeam-forming elements 18 in a set of parallel-connected integratedcircuits 14′ so that the phased array 10A produces a desired beamcharacteristic. For example, control message 93 can be used to perform3D transmit beam steering. Control messages 94 and 95 can be used toadjust the gain settings of a receive beam and a transmit beam,respectively, to compensate for temperature fluctuations. Controlmessages 96 and 97 can be used to perform fast beam switching of areceive beam and a transmit beam, respectively.

FIG. 9 shows an exemplary structure for the register sets shown in thepreceding figures. In this example, the register set 94 a stores anumber of phase shift settings RX_FBS0 to RX_FBS511 with each phaseshift setting for weighting a receive beam. Each of the 512 phase shiftsettings can be stored at a specific address in the register set 94 a,where each address corresponds to one of many beam steering directions(e.g., 512 beam steering directions). All of the beam-forming integratedcircuits 14′ preferably have a related register set configuration sothat receipt of a single address at all of the different beam-formingintegrated circuits 14′ causes each beam-forming integrated circuit 14′to retrieve data from the same address (or cell) in its respectivememory. Although the beam-forming integrated circuits 14′ are retrievingdata from corresponding cells, the actual data in those cells may bedifferent across the integrated circuits 14′ to properly steer the beam.The register set 94 b has a similar configuration in which a number ofphase shift settings TX_FBS0 to TX_FBS511 with each phase shift settingfor weighting a receive beam. Like the receive register set 94 a, eachof the 512 phase shift settings in the transmit register set 94 b isstored at a specific address that corresponds to one of many beamsteering directions (e.g., 512 beam steering directions).

Illustrative embodiments may have similar or different registerstructures for the other functions, such as the phase data,three-dimensional beam steering data, temperature concentration data,and receiver linearity data, among other things.

FIG. 10 shows a process of using the AESA in accordance withillustrative embodiments of the invention. It should be noted that thisprocess is substantially simplified and may have additional steps—it ismerely an example. Accordingly, the process of using the AESA system 10may have many additional steps not discussed. In addition, some of thesteps may be performed in a different order than that shown, or at thesame time. Those skilled in the art therefore can modify the process asappropriate.

The process of FIG. 10 begins at step 1002, in which the processdetermines if changes are necessary to some operating parameter of theAESA system 10. For example, logic may indicate that the direction ofthe beam must be changed. In that case, the process continues to step1004, in which the controller 24 distributes parallel messages to thevarious beam-forming integrated circuits 14′. Those messages may includecontrol data indicating the function to be changed and address dataidentifying the addresses of the registers for the new data. Inillustrative embodiments, those messages are forwarded through theparallel mode data interface ports 62 of the various beam-formingintegrated circuits 14′.

Next, the integrated circuits 14′ extract the register address from themessages at step 1006, and retrieve the data from their respectiveregisters having the address in the message at step 1008. Continuingwith the above example, that retrieved data may include new amplitudeand/or phase information for the beam. At step 1010, the processconcludes when the integrated circuits 14′ apply the retrieved data tothe operation in question. In the above example, the new amplitudeand/or phase information may be applied to the various beam-formingchannels 68 and/or the corresponding beam-forming elements 18, changingthe direction of the transmitted beam.

Accordingly, illustrative embodiments use the parallel-mode data ports62 of the various beam-forming integrated circuits 14 to more rapidlychange operations of the AESA system 10, providing a more robust andresponsive solution.

Although the above discussion discloses various exemplary embodiments ofthe invention, it should be apparent that those skilled in the art canmake various modifications that will achieve some of the advantages ofthe invention without departing from the true scope of the invention.

What is claimed is:
 1. A beamforming integrated circuit comprising:programmable beamforming circuitry including at least one beamformingchannel and at least one programmable beamforming register setassociated with each beamforming channel for storing at least one set ofbeamforming parameters for the beamforming channel; a parallel mode datainput; and a serial data port including a serial data input and a serialdata output allowing the beamforming integrated circuit to be coupledvia the serial data output to the serial data input of a next successivebeamforming integrated circuit in a chain of beamforming integratedcircuits, wherein the beamforming integrated circuit includes a hybridprogramming mode in which the beamforming integrated circuit isconfigured to receive serial messages over the serial data inputcontaining programming data for the beamforming integrated circuit,store programming data for the beamforming integrated circuit receivedin the serial messages in at least one programmable register set,receive a broadcast control command over the parallel mode data inputspecifying a beamforming register set, and switch the programmablebeamforming circuitry to use programming data from the specifiedbeamforming register set in response to the broadcast control command,wherein the broadcast control command causes the beamforming integratedcircuit to switch to the specified beamforming register set insynchronization with other beamforming integrated circuits in the chainswitching to the specified beamforming register set.
 2. A beamformingintegrated circuit according to claim 1, wherein the beamformingintegrated circuit is further configured to transmit the serial messagesvia the serial data output to the next successive beamforming integratedcircuit in the chain so that at least one additional beamformingintegrated circuit in the chain receives programming data required forat least one of its programmable register sets.
 3. A beamformingintegrated circuit according to claim 1, wherein: the at least oneprogrammable beamforming register set associated with each beamformingchannel includes a plurality of programmable beamforming register sets;and the beam steering switch command includes an address identifying theprogrammable beamforming register set to which each beamforming channelis switched.
 4. A beamforming integrated circuit according to claim 3,wherein each programmable beamforming register set includes receiverlinearity data for the beamforming channel.
 5. A beamforming integratedcircuit according to claim 3, wherein each programmable beamformingregister set includes phase data for the beamforming channel.
 6. Abeamforming integrated circuit according to claim 3, wherein eachprogrammable beamforming register set includes gain data for thebeamforming channel.
 7. A beamforming integrated circuit according toclaim 3, wherein each programmable beamforming register set includestemperature compensation data for the beamforming channel.
 8. Abeamforming integrated circuit according to claim 3, wherein eachprogrammable beamforming register set associated with each beamformingchannel stores beamforming parameters with different beamcharacteristics.
 9. A beamforming integrated circuit according to claim1, wherein the parallel mode data input is implemented as a SerialPeripheral Interface (SPI) port.
 10. A beamforming integrated circuitaccording to claim 1, further comprising: at least one programmabletemperature compensation register set for storing temperaturecompensation data for the beamforming integrated circuit received in theserial messages.
 11. A beamforming integrated circuit according to claim1, wherein the beamforming integrated circuit is operable in any of thefollowing three modes: a serial programming mode that uses only theserial data input for managing the programming and switching; a parallelprogramming mode that uses on the parallel mode data input for managingthe programming and switching; and the hybrid programming mode that usesboth the parallel mode data input and the serial data input for managingthe programming and switching.
 12. A phased array system comprising: aplurality of beamforming elements; a plurality of beamforming integratedcircuits according to claim 1 coupled to form the chain, eachbeamforming integrated circuit coupled to at least one of thebeamforming elements for at least one of transmitting or receivingbeamforming signals; and a controller having a parallel mode data outputcoupled to the parallel mode data input of each beamforming integratedcircuit and a serial data output coupled to the serial data input of afirst beamforming integrated circuit of the chain, the controllerconfigured to transmit serial messages over the serial data output tothe serial data input of the first beamforming integrated circuitcontaining programming data for the beamforming integrated circuits andto subsequently transmit a broadcast control command specifying abeamforming register set over the parallel mode data output to cause thebeamforming integrated circuits to switch to the specified beamformingregister set in synchronization.
 13. A system according to claim 12,wherein each beamforming integrated circuit is configured to transmitserial messages received on its serial data input to its serial dataoutput.
 14. A system according to claim 12, wherein: the at least oneprogrammable beamforming register set associated with each beamformingchannel includes a plurality of programmable beamforming register sets;and the broadcast control command includes an address identifying theprogrammable beamforming register set to which each beamforming channelis switched.
 15. A system according to claim 14, wherein eachprogrammable beamforming register set includes receiver linearity datafor the beamforming channel.
 16. A system according to claim 14, whereineach programmable beamforming register set includes phase data for thebeamforming channel.
 17. A system according to claim 14, wherein eachprogrammable beamforming register set includes gain data for thebeamforming channel.
 18. A system according to claim 14, wherein eachprogrammable beamforming register set includes temperature compensationdata for the beamforming channel.
 19. A system according to claim 14,wherein each programmable beamforming register set associated with eachbeamforming channel stores beamforming parameters with different beamcharacteristics.
 20. A system according to claim 12, wherein theparallel mode data input is implemented as a Serial Peripheral Interface(SPI) port.
 21. A system according to claim 12, wherein each beamformingintegrated circuit further comprises at least one programmabletemperature compensation register set for storing temperaturecompensation data for the beamforming integrated circuit received in theserial messages.
 22. A system according to claim 12, wherein eachbeamforming integrated circuit is operable in any of the following threemodes: a serial programming mode that uses only the serial data inputfor managing the programming and switching; a parallel programming modethat uses on the parallel mode data input for managing the programmingand switching; and the hybrid programming mode that uses both theparallel mode data input and the serial data input for managing theprogramming and switching.
 23. A method for controlling beam-formedsignals in a phased array system according to claim 12, the methodcomprising: transmitting, by the controller, serial messages over theserial data output to the serial data input of the first beamformingintegrated circuit containing programming data for the beamformingintegrated circuits; and subsequently transmitting, by the controller, abroadcast control command specifying a beamforming register set over theparallel mode data output to cause the beamforming integrated circuitsto switch to the specified beamforming register set in synchronization.24. A method according to claim 23, wherein: the at least oneprogrammable beamforming register set associated with each beamformingchannel includes a plurality of programmable beamforming register sets;and the broadcast control command includes an address identifying theprogrammable beamforming register set to which each beamforming channelis switched.
 25. A method according to claim 24, wherein the programmingdata includes beamforming parameters with different beam characteristicsfor each programmable beamforming register set associated with eachbeamforming channel.
 26. A method according to claim 23, wherein eachbeamforming integrated circuit further comprises at least oneprogrammable temperature compensation register set and wherein theprogramming data includes temperature compensation data for storage inthe at least one programmable temperature compensation register set.